Pin configuration in master mode,
or when STAC bit is 1
Port 8 pins
P86/SCK1/IRQ5/SCL
P85/RxD1/IRQ4/CS2
P84/TxD1/IRQ3/IOW
P83/IOR
P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (output)
P85 (input/output)/IRQ4 (input)/RxD1 (input)
P84 (input/output)/IRQ3 (input)/TxD1 (output)
P83 (input/output)
Port 8
P82/CS1
P82 (input/output)
P81/GA20
P81 (input/output)
P80/HA0
P80 (input/output)
Pin configuration in slave mode
When STAC bit is 0
P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (input/output)
IRQ4 (input)/CS2 (input)
IRQ3 (input)/IOW (input)
IOR (input)
CS1 (input)
P81 (input/output)/GA20 (output)
HA0 (input)
Figure 7.16 Port 8 Pin Configuration
Register Configuration and Descriptions
7.9.2
Table 7.16 summarizes the port 8 registers.
Table 7.16 Port 8 Registers
Name
Abbreviation
P8DDR
Read/Write
Initial Value
H'80
Address
H'FFBD
H'FFBF
Port 8 data direction register
Port 8 data register
W
P8DR
R/W
H'80
Note: The port 8 data direction register (P8DDR) has the same address as the port B input data
register (PBPIN).
137
HITACHI [ HITACHI SEMICONDUCTOR ]
