Port 7 Input Data Register (P7PIN)
Bit
7
6
5
4
3
2
1
0
P77
—*
R
P76
—*
R
P75
—*
R
P74
—*
R
P73
—*
R
P72
—*
R
P71
—*
R
P70
—*
R
Initial value
Read/Write
Note: * Depends on the levels of pins P77 to P70.
When P7PIN is read, the pin states are always read. P7PIN is a read-only register and cannot be
written to. Write access results in writing to PBDDR.
7.9
Port 8
7.9.1
Overview
Port 8 is a 7-bit input/output port that is multiplexed with host interface (HIF) input pins (HA0,
GA20, CS1, IOR, IOW, CS2), with input/output pins (TxD1, RxD1, SCK1) of serial communication
interface 1, with the I2C clock input/output pin (SCL), and with interrupt input pins (IRQ5 to
IRQ3).
Figure 7.16 shows the pin configuration of port 8. The configuration of the pin functions of pins
P85 and P84 will depend on the value of bit STAC in STCR. Pins P86 and P83 to P80 are unaffected
by bit STAC.
Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor. Pin P86 can be driven as a bus buffer, as shown in section 13, I2C Bus
Interface.
136
HITACHI [ HITACHI SEMICONDUCTOR ]
