ICL232
Test Circuits
C1+
V+
1
2
3
4
5
6
7
8
16
15
14
V
CC
+4.5V TO
+5.5V INPUT
-
+
GND
1µF
C3
C1+
V+
V
1
2
3
4
5
6
7
8
16
CC
C1-
C2+
C2-
T1
OUT
+
1µF
GND 15
R1 13
IN
C1
-
3kΩ
T1
OUT
R1
OUT
12
11
10
9
C1-
C2+
C2-
V-
14
13
12
11
10
9
T1 OUTPUT
RS-232
±30V INPUT
T1
IN
V-
R1
IN
+
1µF
C2
T2
T2
IN
-
OUT
TTL/CMOS
OUTPUT
R1
OUT
1µF C4
-
+
R2
R2
OUT
IN
TTL/CMOS
INPUT
T1
T2
IN
IN
3kΩ
TTL/CMOS
INPUT
R
= V /I T2
IN OUT
T2
OUT
OUT
T2 OUTPUT
V
= ±2V
A
IN
RS-232
±30V INPUT
TTL/CMOS
OUTPUT
R2
OUT
R2
IN
T1
OUT
FIGURE 1. GENERAL TEST CIRCUIT
FIGURE 2. POWER-OFF SOURCE RESISTANCE
CONFIGURATION
Typical Performance Curves
550
10
9
500
V+ (V
= 5V)
CC
o
= 25 C
V- SUPPLY
T
A
450
400
350
300
250
200
150
8
7
6
5
4
3
V+ (V
CC
= 4.5V)
EXTERNAL SUPPLY LOAD
1kΩ BETWEEN V+ + GND
OR V- + GND
TRANSMITTER OUTPUT
OPEN CIRCUIT
V- (V
= 5V)
V- (V
= 4.5V)
CC
CC
GUARANTEED
OPERATING
RANGE
V+ SUPPLY
o
T
= 25 C
A
TRANSMITTER OUTPUTS
OPEN CIRCUIT
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
INPUT SUPPLY VOLTAGE V
(V)
|I
| (mA)
CC
LOAD
FIGURE 3. V+, V- OUTPUT IMPEDANCES vs V
CC
FIGURE 4. V+, V- OUTPUT VOLTAGES vs LOAD CURRENT
Pin Descriptions
PDIP, CERDIP
SOIC
PIN NAME
C1+
V+
DESCRIPTION
1
2
1
2
External capacitor “+” for internal voltage doubler.
Internally generated +10V (typical) supply.
3
3
C1-
External capacitor “-” for internal voltage doubler.
External capacitor “+” internal voltage inverter.
External capacitor “-” internal voltage inverter.
4
4
C2+
C2-
5
5
6
6
V-
Internally generated -10V (typical) supply.
7
7
T2
RS-232 Transmitter 2 output ±10V (typical).
OUT
8
8
R2
RS-232 Receiver 2 input, with internal 5K pulldown resistor to GND.
Receiver 2 TTL/CMOS output.
IN
9
9
R2out
10
11
10
11
T2
T1
Transmitter 2 TTL/CMOS input, with internal 400K pullup resistor to V
.
.
IN
CC
CC
Transmitter 1 TTL/CMOS input, with internal 400K pullup resistor to V
IN
8-51
HARRIS [ HARRIS CORPORATION ]
