HANBit
HSD32M64D8KP
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-75
-10L
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
CLK cycle time
CAS latency=3
CAS latency=3
tCC
7.5
1000
10
1000
ns
ns
1
CLK to valid
output delay
Output data
hold time
tSAC
5.4
6
1,2
CAS latency=3
tOH
3
3
ns
2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
ns
ns
ns
ns
ns
ns
3
3
3
3
3
2
tSS
Input hold time
tSH
CLK to output in Low-Z
CLK to output
tSLZ
tSHZ
CAS latency=3
5.4
6
in Hi-Z
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
L
L
H
X
Entry
Self
3
L
H
X
H
X
H
X
3
3
refres
h
Exit
L
H
X
X
X
X
H
Bank active & row address.
H
L
L
H
H
V
Row address
Auto
disable
precharge
Read &
column
address
Column
Address
(A0 ~ A9)
L
4
H
H
X
X
L
L
H
H
L
L
H
L
X
X
V
V
Auto
disable
Auto
disable
precharge
precharge
H
L
4,5
4
Write &
column
Column
Address
URL:www.hbe.co.kr
- 7 -
HANBiT Electronics Co., Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
