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HSD32M64D8KP-13 参数 Datasheet PDF下载

HSD32M64D8KP-13图片预览
型号: HSD32M64D8KP-13
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组256Mbyte ( 32Mx64bit ) ,无缓冲DIMM与基于堆栈16Mx8 , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on Stacked 16Mx8, 4Banks, 4K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 29 页 / 813 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HSD32M64D8KP  
L
12.8  
Notes:  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).  
AC OPERATING TEST CONDITIONS  
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)  
PARAMETER  
AC Input levels (Vih/Vil)  
Value  
2.4/0.4  
1.4  
UNIT  
V
Input timing measurement reference level  
Input rise and fall time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
+3.3V  
1200W  
V =1.4V  
tt  
DOUT  
V
V
(DC) = 2.4V, I = -2mA  
OH  
OH  
870W  
50pF*  
(DC) = 0.4V, I = 2mA  
OL  
OL  
50W  
DOUT  
Z0=50W  
50pF  
(Fig. 1) DC output load circuit  
(Fig. 2) AC output load circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
VERSION  
PARAMETER  
SYMBOL  
UNIT  
NOTE  
-13  
15  
20  
20  
45  
-10L  
20  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRP(min)  
ns  
ns  
ns  
ns  
1
1
1
1
20  
Row precharge time  
tRP(min)  
20  
tRAS(min)  
tRAS(max)  
50  
Row active time  
100  
ns  
Row cycle time  
tRC(min)  
tRDL(min)  
tDAL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
CAS  
65  
70  
ns  
CLK  
-
1
2
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
2
2 CLK + 20 ns  
1
1
1
CLK  
CLK  
CLK  
2
2
3
Col. address to col. address delay  
Number of valid output data  
URL:www.hbe.co.kr  
2
ea  
4
latency=3  
- 6 -  
HANBiT Electronics Co., Ltd  
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