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GD25Q80CSIG 参数 Datasheet PDF下载

GD25Q80CSIG图片预览
型号: GD25Q80CSIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 56 页 / 1271 K
品牌: GILWAY [ GILWAY TECHNICAL LAMP ]
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3.3V Uniform Sector  
Dual and Quad Serial Flash  
GD25Q80C  
Figure 17.Quad Page Program Sequence Diagram  
CS#  
0
1
2
3
4
5
6
7
8
9 10  
28 29 30 31 32 33 34 35 36 37 38 39  
SCLK  
Command  
32H  
24-bit address  
23 22 21  
MSB  
Byte1 Byte2  
SI(IO0)  
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)  
WP#(IO2)  
HOLD#(IO3)  
CS#  
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55  
Byte11Byte12  
SCLK  
Byte253  
Byte256  
SI(IO0)  
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)  
WP#(IO2)  
HOLD#(IO3)  
7.16. Sector Erase (SE) (20H)  
The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command  
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered  
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid  
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.  
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI   
CS# goes high. The command sequence is shown in Figure 18. CS# must be driven high after the eighth bit of the last  
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven  
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the  
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1  
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is  
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected  
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.  
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