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GD25Q80CSIG 参数 Datasheet PDF下载

GD25Q80CSIG图片预览
型号: GD25Q80CSIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 56 页 / 1271 K
品牌: GILWAY [ GILWAY TECHNICAL LAMP ]
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3.3V Uniform Sector  
Dual and Quad Serial Flash  
GD25Q80C  
7.11. Quad I/O Fast Read (EBH)  
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the  
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each  
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,  
IO1, IO2, IO3. The command sequence is shown in followed Figure 11. The first byte addressed can be at any location.  
The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable  
bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.  
Quad I/O Fast Read with “Continuous Read Mode”  
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read  
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next  
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The  
command sequence is shown in followed Figure 12. If the “Continuous Read Mode” bits (M7-0) are any value other than  
AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read  
Mode” Reset command can be used to reset (M7-0) before issuing normal command.  
Figure 11. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)  
CS#  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23  
SCLK  
Command  
EBH  
SI(IO0)  
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)  
5
6
7
WP#(IO2)  
HOLD#(IO3)  
A23-16 A15-8 A7-0 M7-0  
Dummy  
Byte1 Byte2  
Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)  
CS#  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15  
SCLK  
SI(IO0)  
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SO(IO1)  
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)  
HOLD#(IO3)  
A23-16 A15-8 A7-0 M7-0  
Dummy  
Byte1 Byte2  
22  
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