Table 1-1: Ball List and Description (Continued)
Ball
Name
Timing
Type
Description
J2
EQ_BYPASS
Analog
Input
CONTOL SIGNAL INPUT
Signal levels are 3.3V CMOS / LVTTL compatible.
Equalizer bypass.
When EQ_BYPASS is HIGH, the equalizer stages are bypassed.
When EQ_BYPASS is LOW, normal operation of the equalizer stages
resumes.
J3
JTAG_EN
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are
configured as GSPI pins for normal host interface operation.
J4
CS_TMS
Synchronous
with
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
SCLK_TCK
Chip Select / Test Mode Select
Host Mode (JTAG_EN = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG_EN = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
J5
SDOUT_TDO
Synchronous
with
Output
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
SCLK_TCK
Serial Data Output / Test Data Output
Host Mode (JTAG_EN = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT,
used to read status and configuration information from the
internal registers of the device.
JTAG Test Mode (JTAG_EN = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
J7
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
The DATA_ERROR pin will be LOW when an error within the
received data stream has been detected by the device. This pin is an
inverted logical ‘OR’ing of all detectable errors listed in the internal
ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the
start of the next video frame / field, or until the ERROR_STATUS
register is read via the host interface.
The DATA_ERROR pin will be HIGH when the received data stream
has been detected without error.
NOTE: It is possible to program which error conditions are
monitored by the device by setting appropriate bits in the
ERROR_MASK register HIGH. All error conditions are detected by
default.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
9 of 71
Proprietary & Confidential
38910 - 2
July 2008
GENNUM [ GENNUM CORPORATION ]
