Table 1-1: Ball List and Description (Continued)
Ball
B9
Name
DVB_ASI
Timing
Non
Synchronous
Type
Input /
Output
Description
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This pin and its function are only supported in Manual mode
(AUTO/MAN = LOW).
When the application layer sets this pin HIGH, the device will be
configured to operate in DVB-ASI mode. The SMPTE_BYPASS pin
will be ignored.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
C1, C2
ANA_VDD
Analog
Input
Power
Input
Power
Power supply connection for analog core. Connect to +3.3V DC.
C8, E9, F9, H8
IO_VDD
Non
Synchronous
Power supply for digital I/O.
For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V
DC.
For a 5V tolerant I/O, connect pins to a +3.3V DC.
D1, D2
ANA_GND
Analog
Input
Power
Input
Power
Input
Power
Ground connection for analog core. Connect to GND.
D4, D5, E4,
E5, F4, F5, G4,
G5
D6, D7, E6,
E7, F6, F7, G6,
G7
E1
CORE_GND
Non
Synchronous
Ground connection for digital logic blocks. Connect to GND.
IO_GND
Non
Synchronous
Ground connection for digital I/O. Connect to GND.
EQ_GND
Analog
Input
Power
Input
Input
Input
Power
Input
Power
Input
Ground connection for equalizer core. Connect to GND.
E2
F1, G1
F2, F3, G2,
G3, H2, H3
H1
TERM
SDI, SDI
HEAT_SINK_GND
Analog
Analog
Analog
Termination for serial digital input. AC couple to ANA_GND
Serial digital differential input pair.
Heat sink connection. Connect to main ground plane of application
board.
Power supply connection for equalizer core. Connect to +3.3V DC.
EQ_VDD
Analog
H9
RD_RESET
Synchronous
with RD_CLK
FIFO READ RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH and DVB-ASI = LOW), and the internal FIFO is configured
for video mode (Section
A HIGH to LOW transition will reset the FIFO pointer to address
zero of the memory.
J1, K1
AGC+, AGC-
Analog
Input
External AGC capacitor connection. Connect J1 and K1 together
through a 1uF capacitor.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
8 of 71
Proprietary & Confidential
GENNUM [ GENNUM CORPORATION ]
