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GS9091BCBE3 参数 Datasheet PDF下载

GS9091BCBE3图片预览
型号: GS9091BCBE3
PDF下载: 下载PDF文件 查看货源
内容描述: GenLINX II 270MB / s的解串器的SDI和DVB -ASI [GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI]
分类和应用:
文件页数/大小: 71 页 / 667 K
品牌: GENNUM [ GENNUM CORPORATION ]
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Table 1-1: Ball List and Description (Continued)  
Ball  
Name  
Timing  
Type  
Description  
K3  
IOPROC_EN  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal Levels are LVCMOS / LVTTL compatible.  
Used to enable or disable the I/O processing features.  
When set HIGH, the following I/O processing features of the device  
are enabled:  
• Illegal Code Remapping  
• EDH CRC Error Correction  
• Ancillary Data Checksum Error Correction  
• TRS Error Correction  
• EDH Flag Detection  
To enable a subset of these features, keep IOPROC_EN HIGH and  
disable the individual feature(s) in the IOPROC_DISABLE register  
accessible via the host interface.  
When set LOW, the device will enter low-latency mode.  
NOTE: When the internal FIFO is configured for Video mode or  
Ancillary Data Extraction mode, IOPROC_EN must be set HIGH (see  
Section 3.10).  
K4  
RESET  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS / LVTTL compatible.  
Used to reset the internal operating conditions to default setting  
or to reset the JTAG test sequence.  
Host Mode (JTAG_EN = LOW):  
When asserted LOW, all functional blocks will be set to default  
conditions and all input and output signals become high  
impedance.  
When set HIGH, normal operation of the device resumes 10usec  
after the LOW-to-HIGH transition of the RESET signal.  
JTAG Test Mode (JTAG_EN = HIGH):  
When asserted LOW, all functional blocks will be set to default and  
the JTAG test sequence will be held in reset.  
When set HIGH, normal operation of the JTAG test sequence  
resumes.  
K5  
SCLK_TCK  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS / LVTTL compatible.  
Serial Data Clock / Test Clock. All JTAG / Host Interface address and  
data are shifted into/out of the device synchronously with this  
clock.  
Host Mode (JTAG_EN = LOW):  
SCLK_TCK operates as the host interface serial data clock, SCLK.  
JTAG Test Mode (JTAG_EN = HIGH):  
SCLK_TCK operates as the JTAG test clock, TCK.  
GS9091B GenLINX® II 270Mb/s Deserializer for SDI  
and DVB-ASI  
Data Sheet  
10 of 71  
Proprietary & Confidential  
38910 - 2  
July 2008