Table 1-1: Ball List and Description (Continued)
Ball
Name
Timing
Type
Description
K6
SDIN_TDI
Synchronous
with
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
SCLK_TCK
Serial Data Input / Test Data Input
Host Mode (JTAG_EN = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG_EN = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
K7, K8, J8, J9
STAT[0:3]
Synchronous
with PCLK or
RD_CLK
Output
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function outputs. By programming the bits is
the IO_CONFIG register, each pin can output one of the following
signals:
• H
• V
• F
• FIFO_LD
• ANC
• EDH_DETECT
• FIFO_FULL
• FIFO_EMPTY
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected.
See Section 3.12 for details.
K9
RD_CLK
–
Input
FIFO READ CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The application layer clocks the parallel data out of the FIFO on the
rising edge of RD_CLK.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
11 of 71
Proprietary & Confidential
38910 - 2
July 2008
GENNUM [ GENNUM CORPORATION ]
