GS9090 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
23, 25, 26, 27
STAT[0:3]
Synchronous
with PCLK or
RD_CLK
Output
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function outputs. By programming the bits is the
IO_CONFIG register, each pin can output one of the following signals:
•
•
•
•
•
•
•
•
H
V
F
FIFO_LD
ANC_DETECT
EDH_DETECT
FIFO_FULL
FIFO_EMPTY
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected. See
Programmable Multi-Function Outputs on page 56 for details.
24, 28, 42
30
IO_GND
RD_CLK
Non
Synchronous
Input
Power
Ground connection for digital I/O. Connect to GND.
–
Input
FIFO READ CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The application layer clocks the parallel data out of the FIFO on the
rising edge of RD_CLK.
31
RD_RESET
Synchronous
with RD_CLK
Input
FIFO READ RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH and DVB-ASI = LOW), and the internal FIFO is configured for
video mode (see Video Mode on page 46).
A HIGH to LOW transition will reset the FIFO pointer to address zero of
the memory.
32 - 41
DOUT[0:9]
Synchronous
withRD_CLK
or PCLK
Output
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked out of the device
on the rising edge of RD_CLK.
When the internal FIFO is in bypass mode, parallel data will be clocked
out of the device on the rising edge of PCLK.
DOUT9 is the MSB and DOUT0 is the LSB.
44
PCLK
–
Output
PIXEL CLOCK OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock output.
28201 - 1 July 2005
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