GS9090 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Name
Timing
Type
Description
Number
1
LF-
Analog
Analog
Input
Loop filter component connection. Connect to pin 56 (LF+) as shown in
the Typical Application Circuit (Part B) on page 67.
2
PLL_GND
Input
Ground connection for phase-locked loop. Connect to GND.
Power supply connection for phase-locked loop. Connect to +1.8V DC.
Power supply connection for digital input buffers.
Power
3
4
PLL_VDD
Analog
Analog
Input
Power
BUFF_VDD
Input
Power
When operating with 1.8V input as required by the current silicon this
pin should be left unconnected.
When operating with 3.3V input (available in future silicon) this pin
should be connected to +3.3V as shown in the Typical Application
Circuit (Part B) on page 67.
5, 6
7
DDI, DDI
Analog
Analog
Input
Serial digital differential input pair.
BUFF_GND
Input
Ground connection for serial digital input buffer. Connect to GND.
Power
8
TERM
NC
Analog
–
Input
–
Termination for serial digital input. AC couple to BUFF_GND
No connect.
9, 11
10
VBG
Analog
Input
Bandgap filter capacitor. Connect to GND as shown in the Typical
Application Circuit (Part B) on page 67.
12
IOPROC_EN
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
•
•
•
•
•
Illegal Code Remapping
EDH CRC Error Correction
Ancillary Data Checksum Error Correction
TRS Error Correction
EDH Flag Detection
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for Video mode or
Ancillary Data Extraction mode, the IOPROC_EN pin must be set
HIGH (see Internal FIFO Operation on page 46).
28201 - 1 July 2005
6 of 70
GENNUM [ GENNUM CORPORATION ]
