GS9090 Data Sheet
Data-Through mode, and the internal reclocker locks to the data stream, the
LOCKED pin will be set HIGH.
If the application layer does not set the AUTO/MAN pin LOW, the GS9090 will set
the SMPTE_BYPASS and DVB_ASI signals to logic LOW if presented with a data
stream without SMPTE TRS ID words or DVB-ASI sync words. In addition, the
LOCKED pin and data bus output pins will be forced LOW.
3.9 Additional Processing Features
The GS9090 contains additional processing features that are available in SMPTE
mode only (see SMPTE Functionality on page 25).
3.9.1 FIFO Load Pulse
To aid in the implementation of auto-phasing and line synchronization functions,
the GS9090 will generate a FIFO load pulse to reset line-based FIFO storage. This
FIFO_LD signal is available for output on one of the multi-function output port pins,
if so programmed (see Programmable Multi-Function Outputs on page 56).
The FIFO_LD pulse will normally be HIGH, but will go LOW for one PCLK period,
thereby generating a FIFO write reset signal.
By default, the FIFO load pulse will be generated such that it is co-timed to the SAV
XYZ code word presented to the output data bus. This co-timing ensures that the
next PCLK cycle will correspond with the first active sample of the video line.
NOTE: When the internal FIFO of the GS9090 is set to operate in video mode, the
FIFO_LD pulse can be used to drive the RD_RESET input to the device (see Video
Mode on page 46).
Figure 3-4 shows the default timing relationship between the FIFO_LD signal and
the output video data.
PCLK
Y'CbCr DATA
FIFO_LD
XYZ
3FF
000
000
Figure 3-4: FIFO_LD Pulse Timing
3.9.1.1 Programmable FIFO Load Position
The position of the FIFO_LD pulse can be moved in PCLK increments from its
default position to a maximum of one full line. The offset number of PCLK's must
be programmed in the FIFO_LD_POSITION[12:0] internal register (address 28h),
via the host interface.
28201 - 1 July 2005
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