GS9090 Data Sheet
3.9.3 EDH Packet Detection
The GS9090 will determine if EDH packets are present in the incoming video data
and assert the EDH_DETECT output status signal appropriately.
EDH_DETECT will be set HIGH when EDH packets have been detected and will
remain HIGH until EDH packets are no longer present. The signal will be set LOW
at the end of the vertical blanking (falling edge of V) if an EDH packet has not been
received and detected during vertical blanking.
EDH_DETECT is available for output on the multi-function output port pins, if so
programmed (see Programmable Multi-Function Outputs on page 56).
Additionally, the EDH_DETECT bit is stored in the DATA_FORMAT register at
address 04h (see Table 3-7).
3.9.4 EDH Flag Detection
As described in EDH Packet Detection on page 33, the GS9090 can detect EDH
packets in the received data stream. The EDH flags for ancillary data, active
picture, and full field areas are extracted from the detected EDH packets and
placed in the EDH_FLAG_IN register of the device (Table 3-5).
When the EDH_FLAG_UPDATE bit in the DATA_FORMAT register (Table 3-7) is
set HIGH by the application layer, the GS9090 will update the ancillary data, full
field, and active picture EDH flags according to SMPTE RP165. The updated EDH
flags are placed in the EDH_FLAG_OUT register (Table 3-6). The EDH packet
output from the device will contain the updated flags.
One set of flags is provided for both fields 1 and 2. Field 1 flag data will be
overwritten by field 2 flag data.
When no EDH packets are detected (EDH_DETECT = LOW), the UES flags in the
EDH_FLAG_OUT register will be set HIGH to signify that the received signal does
not support the error detection practice. These flags are set regardless of the
setting of the EDH_FLAG_UPDATE bit.
NOTE: When EDH_FLAG_UPDATE is LOW with EDH packets in the video
stream, the content of the EDH_FLAG_OUT register is not valid and should be
ignored.
Both EDH_FLAG registers may be read by the host interface at any time during the
received frame except on the lines defined in SMPTE RP165 where these flags are
updated.
The GS9090 will also extract the CRC valid or ‘V’ bit for both active picture and full
field CRCs. The AP_CRC_V bit in the DATA_FORMAT register provides the active
picture CRC valid bit status, and the FF_CRC_V bit provides the full field CRC valid
bit status (see Table 3-7). When EDH_DETECT = LOW, these bits will be cleared.
The flag register values remain set until overwritten by the decoded flags in the
next received EDH packet in the following field. When no EDH packet is detected
during vertical blanking, the flag registers will be cleared at the end of the vertical
blanking period.
28201 - 1 July 2005
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