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GS9060-CF 参数 Datasheet PDF下载

GS9060-CF图片预览
型号: GS9060-CF
PDF下载: 下载PDF文件 查看货源
内容描述: HD - LINX II SD- SDI和DVB- ASI解串器,带环通电缆驱动器 [HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 61 页 / 885 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9060 Data Sheet  
Table 1-1: Pin Descriptions (Continued)  
Pin  
Name  
Timing  
Type  
Description  
Number  
13  
IOPROC_EN/DIS  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
Used to enable or disable I/O processing features.  
When set HIGH, the following I/O processing features of the  
device are enabled:  
EDH CRC Error Correction  
ANC Data Checksum Correction  
TRS Error Correction  
Illegal Code Remapping  
To enable a subset of these features, keep IOPROC_EN/DIS  
HIGH and disable the individual feature(s) in the  
IOPROC_DISABLE register accesible via the host interface.  
When set LOW, the I/O processing features of the device are  
disabled, regardless of whether the features are enabled in the  
IOPROC_DISABLE register.  
14  
CD2  
Non  
Input  
STATUS SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
Used to indicate the presence of a serial digital input signal.  
Normally generated by a Gennum automatic cable equalizer.  
When LOW, the serial digital input signal received at the DDI2  
and DDI2 pins is considered valid.  
When HIGH, the associated serial digital input signal is  
considered to be invalid. In this case, the LOCKED signal is set  
LOW and all parallel outputs are muted.  
15,17  
16  
DDI_2, DDI_2  
TERM2  
Analog  
Analog  
Input  
Input  
Differential input pair for serial digital input 2.  
Termination for serial digital input 2. AC couple to  
PDBUFF_GND.  
18  
SMPTE_BYPASS  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
When set HIGH in conjunction with DVB_ASI = LOW, the device  
will be configured to operate in SMPTE mode. All I/O processing  
features may be enabled in this mode.  
When set LOW, the device will not support the descrambling,  
decoding or word alignment of received SMPTE data. No I/O  
processing features will be available.  
19  
20  
RSET  
Analog  
Input  
Used to set the serial digital loop-through output signal  
amplitude. Connect to CD_VDD through 281+/- 1% for  
800mVp-p single-ended output swing.  
CD_VDD  
Power  
Power supply connection for the serial digital cable driver.  
Connect to +1.8V DC analog.  
22208 - 8 January 2007  
7 of 61  
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