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GS9060-CF 参数 Datasheet PDF下载

GS9060-CF图片预览
型号: GS9060-CF
PDF下载: 下载PDF文件 查看货源
内容描述: HD - LINX II SD- SDI和DVB- ASI解串器,带环通电缆驱动器 [HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 61 页 / 885 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9060 Data Sheet  
Table 1-1: Pin Descriptions (Continued)  
Pin  
Name  
Timing  
Type  
Description  
Number  
33, 68  
34  
CORE_GND  
F
Power  
Output  
Ground connection for the digital core logic. Connect to digital  
GND.  
Synchronous  
with PCLK  
STATUS SIGNAL OUTPUT  
Signal levels are LVCMOS/LVTTL compatible.  
Used to indicate the ODD / EVEN field of the video signal.  
The F signal will be HIGH for the entire period of field 2 as  
indicated by the F bit in the received TRS signals.  
The F signal will be LOW for all lines in field 1 and for all lines in  
progressive scan systems.  
35  
V
Synchronous  
with PCLK  
Output  
STATUS SIGNAL OUTPUT  
Signal levels are LVCMOS/LVTTL compatible.  
Used to indicate the portion of the video field / frame that is used  
for vertical blanking.  
The V signal will be HIGH for the entire vertical blanking period  
as indicated by the V bit in the received TRS signals.  
The V signal will be LOW for all lines outside of the vertical  
blanking interval.  
36  
H
Synchronous  
with PCLK  
Output  
STATUS SIGNAL OUTPUT  
Signal levels are LVCMOS/LVTTL compatible.  
Used to indicate the portion of the video line containing active  
video data. H signal timing is configurable via the H_CONFIG bit  
of the IOPROC_DISABLE register accessible via the host  
interface.  
Active Line Blanking (H_CONFIG = 0h)  
The H signal will be HIGH for the entire horizontal blanking  
period, including the EAV and SAV TRS words, and LOW  
otherwise. This is the default setting.  
TRS Based Blanking (H_CONFIG = 1h)  
The H signal will be HIGH for the entire horizontal blanking period  
as indicated by the H bit in the received TRS ID words, and LOW  
otherwise.  
37, 64  
CORE_VDD  
DOUT[0:9]  
Power  
Output  
Power supply connection for the digital core logic. Connect to  
+1.8V DC digital.  
38, 39, 42–  
48, 50  
Synchronous  
with PCLK  
PARALLEL DATA BUS  
Signal levels are LVCMOS/LVTTL compatible.  
DOUT9 is the MSB and DOUT0 is the LSB.  
20-bit mode  
20bit/10bit = HIGH  
Chroma data output in SMPTE mode  
SMPTE_BYPASS = HIGH  
DVB_ASI = LOW  
Data output in Data-Through mode  
SMPTE_BYPASS = LOW  
DVB_ASI = LOW  
Forced LOW in DVB-ASI mode  
SMPTE_BYPASS = LOW  
DVB_ASI = HIGH  
10-bit mode  
Forced LOW in all modes.  
20bit/10bit = LOW  
22208 - 8 January 2007  
10 of 61  
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