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GS9060-CF 参数 Datasheet PDF下载

GS9060-CF图片预览
型号: GS9060-CF
PDF下载: 下载PDF文件 查看货源
内容描述: HD - LINX II SD- SDI和DVB- ASI解串器,带环通电缆驱动器 [HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 61 页 / 885 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9060 Data Sheet  
Contents  
Key Features.................................................................................................................1  
Applications...................................................................................................................1  
Description ....................................................................................................................1  
Functional Block Diagram .............................................................................................2  
1. Pin Out .....................................................................................................................5  
1.1 Pin Assignment...............................................................................................5  
1.2 Pin Descriptions..............................................................................................6  
2. Electrical Characteristics........................................................................................14  
2.1 Absolute Maximum Ratings ..........................................................................14  
2.2 DC Electrical Characteristics ........................................................................14  
2.3 AC Electrical Characteristics.........................................................................16  
2.4 Solder Reflow Profiles...................................................................................18  
2.5 Input/Output Circuits .....................................................................................19  
2.6 Host Interface Map........................................................................................21  
2.6.1 Host Interface Map (R/W registers) ...................................................22  
2.6.2 Host Interface Map (Read only registers) ..........................................23  
3. Detailed Description...............................................................................................24  
3.1 Functional Overview .....................................................................................24  
3.2 Serial Digital Input.........................................................................................24  
3.2.1 Input Signal Selection.........................................................................24  
3.2.2 Carrier Detect Input ............................................................................25  
3.2.3 Single Input Configuration ..................................................................25  
3.3 Serial Digital Reclocker.................................................................................25  
3.3.1 External VCO......................................................................................26  
3.3.2 Loop Bandwidth..................................................................................26  
3.4 Serial Digital Loop-Through Output ..............................................................26  
3.4.1 Output Swing ......................................................................................26  
3.4.2 Reclocker Bypass Control ..................................................................27  
3.4.3 Serial Digital Output Mute...................................................................27  
3.5 Serial-To-Parallel Conversion.......................................................................28  
3.6 Lock Detect...................................................................................................28  
3.6.1 Input Control Signals ..........................................................................29  
3.7 SMPTE Functionality ....................................................................................30  
3.7.1 SMPTE Descrambling and Word Alignment.......................................30  
3.7.2 Internal Flywheel.................................................................................30  
3.7.3 Switch Line Lock Handling..................................................................31  
3.7.4 HVF Timing Signal Generation...........................................................33  
3.8 DVB-ASI Functionality ..................................................................................34  
3.8.1 Transport Packet Format....................................................................35  
3.8.2 DVB-ASI 8b/10b Decoding and Word Alignment................................35  
22208 - 8 January 2007  
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