GS9060 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Name
Timing
Type
Description
Number
1
2
3
4
5
CP_VDD
PDBUFF_GND
PD_VDD
BUFF_VDD
CD1
–
–
–
–
Power
Power
Power
Power
Input
Power supply connection for the charge pump. Connect to +3.3V
DC analog.
Ground connection for the phase detector and serial digital input
buffers. Connect to analog GND.
Power supply connection for the phase detector. Connect to
+1.8V DC analog.
Power supply connection for the serial digital input buffers.
Connect to +1.8V DC analog.
Non
STATUS SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal.
Normally generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI1
and DDI1 pins is considered valid.
When HIGH, the associated serial digital input signal is
considered to be invalid. In this case, the LOCKED signal is set
LOW and all parallel outputs are muted.
6,8
7
DDI1, DDI1
TERM1
Analog
Analog
Input
Input
Differential input pair for serial digital input 1.
Termination for serial digital input 1. AC couple to
PDBUFF_GND.
9
DVB_ASI
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SMPTE_BYPASS = LOW, the
device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
10
IP_SEL
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital
input signal, and CD1 or CD2 as the carrier detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the serial digital input
and CD1 is selected as the carrier detect input signal.
When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier
detect input signal is selected.
11
12
NC
–
–
No Connect.
20bit/10bit
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to select the output data bus width in SMPTE or
Data-Through modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will be 20-bit demultiplexed
data.
When set LOW, the parallel outputs will be 10-bit multiplexed
data.
22208 - 8 January 2007
6 of 61
GENNUM [ GENNUM CORPORATION ]
