GS9060 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
67
FW_EN/DIS
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the
device.
When set HIGH, the internal flywheel is enabled. This flywheel is
used in the extraction and generation of TRS timing signals, in
automatic video standards detection, and in manual switch line
lock handling.
When set LOW, the internal flywheel is disabled and TRS
correction and insertion is unavailable.
69
70
PCLK
–
Output
Input
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
20-bit mode
PCLK = 13.5MHz
PCLK = 27MHz
10-bit mode
RC_BYP
Non
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH, the serial digital output will be a reclocked
version of the input signal regardless of whether the device is in
SMPTE, DVB-ASI or Data-Through mode.
When set LOW, the serial digital output will be a buffered version
of the input signal in all modes.
71
72
NC
–
–
No connect.
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has
correctly received and locked to SMPTE compliant data in
SMPTE mode or DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
73, 74
VCO, VCO
VCO_GND
Analog
Input
Differential inputs for the external VCO reference signal. For
single ended devices such as the GO1555/GO1525*, VCO
should be AC coupled to VCO_GND.
*For new designs use GO1555
75
–
Output Power
Ground reference for the external voltage controlled oscillator.
Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin
is an output.
Should be isolated from all other grounds.
*For new designs use GO1555
22208 - 8 January 2007
12 of 61
GENNUM [ GENNUM CORPORATION ]
