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GS9020ACTVE3 参数 Datasheet PDF下载

GS9020ACTVE3图片预览
型号: GS9020ACTVE3
PDF下载: 下载PDF文件 查看货源
内容描述: GENLINX -TM II GS9020A串行数字视频输入处理器 [GENLINX -TM II GS9020A Serial Digital Video Input Processor]
分类和应用: 消费电路商用集成电路
文件页数/大小: 31 页 / 403 K
品牌: GENNUM [ GENNUM CORPORATION ]
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3.10 Flag Port  
CLR1  
CLR0  
MODE OF OPERATION  
Normal  
0
0
1
1
0
1
0
1
PIN  
LOGIC OPR  
HOST BIT  
Reset Counter to Zero  
Auto Reset  
F_R/W  
S[1:0]  
FL[4:0]  
Hold Counter at Zero  
>
OVERWRITE VALUES  
In "Normal" mode the counter operates as previously  
discussed, such that the counter increments on detection of  
any error for which the sensitivity flags are set HIGH. If  
“Reset Counter to Zero” mode is selected, the counter is  
reset to zero and begins counting again. The mode of  
operation will immediately return to 00 (normal mode) once  
the counter resets. In "Auto Reset" mode, the counter  
behaves in the normal fashion, except that it resets to zero  
every time a HOSTIF read of the lowest 8 bits of the error  
counter (address 17) is performed. This functionality allows  
the chip to count the number of errors since the last read.  
The “Hold Counter at Zero” mode instantly freezes the  
counter at zero until it is moved into one of the other modes.  
In addition to the HOSTIF tables, the EDH error flags can  
also be read and written via the synchronous flag port. The  
five flag port pins, FL[4:0], allow access to all 15 error flags.  
The select pins S[1:0] control which flags are read/written  
as outlined below. If the flag port is not going to be used, it  
is best to set F_R/W high, leave FL[4:0] unconnected, and  
set S[1:0] to any value desired (but not floating).  
3.10.1 Write Mode  
When the F_R/W pin is LOW, the flag port is in write mode  
and the FL[4:0] pins are configured as inputs. After writing  
to the flag port, the GS9020A inserts the written flags into  
the next outgoing EDH packet. Note that external flag  
overwriting via the flag port takes precedence over HOSTIF  
overwriting but the flag port writing only affects the next  
outgoing EDH packet. Following this, if the flag port is not  
written to again, flag operation is returned to normal EDH  
functionality (unless it is being overwritten through the  
HOSTIF).  
3. 9 INTERRUPT Signal  
PIN  
LOGIC OPR  
HOST BIT  
INTERRUPT  
The data present on the FL[4:0] output pins, as controlled  
by the S[1:0] pins, is summarized below.  
An interrupt output pin (INTERRUPT) is also available on the  
GS9020A. The INTERRUPT output is asserted LOW for  
each field that contains errors in the outgoing EDH packet.  
The sensitivity flags used for the 24 bit errored field counter  
also apply to the interrupt signal. As a result, the interrupt  
can be made sensitive to any particular flags. The  
INTERRUPT signal is stable after an EDH packet exits the  
device and before the subsequent EDH packet enters the  
device as shown in Figure 11.  
Write Mode, F_R/W = 0  
S[1:0]  
00  
FL4  
FL3  
FL2  
FL1  
FL0  
FF UES  
AP UES  
FF IDA  
AP IDA  
FF IDH  
AP IDH  
FF EDA  
AP EDA  
FF EDH  
AP EDH  
01  
10  
ANC  
UES  
ANC  
IDA  
ANC  
IDH  
ANC  
EDA  
ANC  
EDH  
If the STICKY OUT control bit is asserted HIGH, the  
interrupt remains asserted LOW until a HOSTIF read is  
performed on the flag that caused the interrupt.  
11  
IN/OUT  
APV  
FFV  
0
0
The INTERRUPT output is an open drain output and as a  
result requires an external pull-up resistor. A 10k resistor  
value is recommended. If this output is not used, a pullup  
resistor is not required.  
In addition to overwriting the 15 error flags, the outgoing  
validity bits for the active picture (APV) and full field (FFV)  
can be overwritten via the flag port.  
The IN/OUT bit has no effect on writes to the error flags. IN/  
OUT is a control bit used to determine if the flags read from  
the flag port during flag port read cycles represent  
incoming or outgoing EDH flags. If this bit is set HIGH, all  
subsequent reads are from the incoming EDH packet. If this  
bit is set LOW, then all subsequent reads are from the  
updated outgoing packet. When the IN/OUT bit is written to,  
the value remains latched until it is re-programmed. The IN/  
OUT bit is set LOW upon reset of the chip.  
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