GS4915 Data Sheet
3.5 Output Clock Frequency and Jitter
The frequency and jitter of the output clock are determined by:
the frequency of the input clock,
the differential or single-ended input and output clocks,
•
•
•
•
•
the selected frequency mode,
the selected bypass mode, and
the setting of the DOUBLE pin.
When the DOUBLE pin is set HIGH, the output clock frequency will be double the
input only when the selected input clock frequency is determined to be 74.25MHz
± 0.4%. Otherwise, the setting of the DOUBLE pin will have no effect on the
frequency of the output clock.
The output clock will be low jitter when the LOCK pin is HIGH. The only exception
to this is if operating in Manual Bypass mode, see Section 3.4.2.Table 3-4,
Table 3-5, and Table 3-6 summarize the output frequency and LOCK behaviour of
the device given the frequency of the input clock, the selected frequency mode,
and the setting of the DOUBLE pin for Autobypass, Manual Bypass, and Forced
Output modes, respectively. In each table, 'X' indicates a "don't care" condition.
Table 3-4: Output Behaviour in Autobypass Mode
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Auto [00]
27MHz
X
0
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
27MHz
74.25MHz
148.5MHz
148.5MHz
Input
74.25MHz
1
148.5MHz
Other
X
X
X
X
X
X
X
0
Fixed – 27MHz
[01]
27MHz
27MHz
74.25MHz
148.5MHz
Other
74.25MHz
148.5MHz
Input
Fixed –
74.25MHz [10]
27MHz
27MHz
74.25MHz
74.25MHz
148.5MHz
148.5MHz
Input
1
148.5MHz
Other
X
X
X
X
X
X
Fixed –
148.5MHz [11]
27MHz
27MHz
74.25MHz
148.5MHz
Other
74.25MHz
148.5MHz
Input
39145 - 3 November 2007
18 of 26
GENNUM [ GENNUM CORPORATION ]
