GS4915 Data Sheet
3.3.4 External VCO
The GS4915 uses the external GO1555 Voltage Controlled Oscillator as part of its
phase-locked loop. This external VCO implementation was chosen to ensure
superior jitter performance of the device.
Power for the external VCO is generated entirely by the GS4915 from an on-chip
voltage regulator. The internal regulator uses +3.3V DC supplied at the REG_VDD
pin to provide +2.5V at the VCO_VDD pin.
Based on the control voltage output by the GS4915 on the LF pin, the GO1555
produces a 1.485GHz reference signal for the PLL. This signal must be run via a
50Ω controlled-impedance trace to the VCO pin of the GS4915. The VCO receiver
block of the device will then convert this single-ended signal into the differential
1.485GHz reference signal used by the clock cleaning PLL.
Both the reference and controls signals should be referenced to the supplied
VCO_GND, as shown in the recommended application circuit of the Typical
Application Circuit on page 22.
3.4 Modes of Operation
The GS4915 may operate in one of two possible frequency modes, and in one of
three possible bypass modes. The combination of the frequency mode and bypass
mode will determine the frequency and jitter of the output clock.
3.4.1 Frequency Modes
The frequency mode of the device is determined entirely by the setting of the
external FCTRL[1:0] pins.
Table 3-2: GS4915 Frequency Modes
FCTRL[1:0]
Frequency Mode
00
01
10
11
Auto
Fixed – 27MHz ± 0.4%
Fixed – 74.25MHz ± 0.4%
Fixed – 148.5MHz ± 0.4%
In both Auto and Fixed Frequency modes, the GS4915 will measure the selected
input clock frequency to determine if it is in any of the following ranges: 27MHz ±
0.4%, 74.25MHz ± 0.4%, or 148.5MHz ± 0.4% (these ranges include the
74.25MHz/1.001 and 148.5MHz/1.001 video clock frequencies).
39145 - 3 November 2007
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