GS4915 Data Sheet
Table 3-6: Output Behaviour in Forced Output Mode (Continued)
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Fixed –
74.25MHz [10]
27MHz
0
1
0
1
0
1
0
1
X
X
X
X
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
74.25MHz
148.5MHz
74.25MHz
148.5MHz
74.25MHz
148.5MHz
74.25MHz
148.5MHz
148.5MHz
148.5MHz
148.5MHz
148.5MHz
74.25MHz
148.5MHz
Other
Fixed –
148.5MHz [11]
27MHz
74.25MHz
148.5MHz
Other
*NOTE: The output clock will remain within ± 5% of the last locked frequency if an input frequency
other than 27MHz, 74.25MHz, or 148.5MHz is applied to the selected clock input. If operating
under these conditions upon power-up, the output frequency will be 74.25MHz ± 5%.
3.6 Output Skew
The GS4915 provides the user with the option of advancing the phase of the output
clock from that of the input clock. This feature is controlled by the external
SKEW_EN pin.
When SKEW_EN is set LOW, the output clock will be delayed from the selected
input clock only by the latency of the device. By setting SKEW_EN = HIGH, the
user can advance the output clock from the selected input clock by one quarter of
an output period, minus the latency of the device. Please see Figure 3-2.
Input Clock
Output Clock
Device Latency
1/4 CLK Period - Device Latency
SKEW_EN = LOW
SKEW_EN = HIGH
Figure 3-2: Output skew behaviour of GS4915
39145 - 3 November 2007
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GENNUM [ GENNUM CORPORATION ]
