GS1560A/GS1561 Data Sheet
Table 3-13: Host Interface Description for EDH Calculation Range Registers (Continued)
Register Name
Bit
Name
Description
R/W Default
FF_LINE_END_F1
Address: 019h
15-10
9-0
–
Not Used.
–
–
0
FF_LINE_END_F1[9:0]
Field 1 Full Field end line data used to set EDH
calculation range outside of SMPTE RP 165 values.
R/W
3.10.5.3 Lock Error Detection
The LOCKED pin of the GS1560A/GS1561 indicates the lock status of the
reclocker and lock detect blocks of the device. Only when the LOCKED pin is
asserted HIGH has the device correctly locked to the received data stream, (see
Lock Detect on page 35).
The GS1560A/GS1561 will also indicate lock error to the host interface when
LOCKED = LOW by setting the LOCK_ERR bit in the ERROR_STATUS register
HIGH.
3.10.5.4 Ancillary Data Checksum Error Detection
The GS1560A/GS1561 will calculate checksums for all received ancillary data and
compare the calculated values to the received checksum words. If a mismatch is
detected, the error is flagged in the CCS_ERR and/or YCS_ERR bits of the
ERROR_STATUS register.
When operating in HD mode, (SD/HD = LOW), the device will make comparisons
on both the Y and C channels separately. If an error condition in the Y channel is
detected, the YCS_ERR bit will be set HIGH. If an error condition in the C channel
is detected, the CCS_ERR bit will be set HIGH.
When operating in SD mode, (SD/HD = HIGH), only the YCS_ERR bit will be set
HIGH when checksum errors are detected.
Although the GS1560A/GS1561 will calculate and compare checksum values for
all ancillary data types by default, the host interface may program the device to
check only certain types of ancillary data checksums.
This is accomplished via the ANC_TYPE register as described in Programmable
Ancillary Data Detection on page 50.
27360 - 8 September 2005
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