GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
31
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the received
data stream has been detected by the device. This pin is a logical 'OR'ing
of all detectable errors listed in the internal ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the start
of the next video frame / field, or until the ERROR_STATUS register is
read via the host interface.
The DATA_ERROR signal will be HIGH when the received data stream
has been detected without error.
NOTE: It is possible to program which error conditions are monitored by
the device by setting appropriate bits of the ERROR_MASK register HIGH.
All error conditions are detected by default.
32
FIFO_LD
Synchronous
with PCLK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
33, 68
34
CORE_GND
F
–
Power
Output
Ground connection for the digital core logic. Connect to digital GND.
Synchronous
with PCLK
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated by the
F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
35
V
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
36
H
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data.
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW otherwise.
37, 64
CORE_VDD
–
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
27360 - 8 September 2005
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GENNUM [ GENNUM CORPORATION ]
