GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
70
RC_BYP
Non
Input
GS1560A
Synchronous
/Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The RC_BYP signal will be HIGH only when the device has successfully
locked to a SMPTE or DVB-ASI compliant input data stream. In this case,
the serial digital loop-through output will be a reclocked version of the
input.
The RC_BYP signal will be LOW whenever the input does not conform to
a SMPTE or DVB-ASI compliant data stream. In this case, the serial digital
loop-through output will be a buffered version of the input.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH, the serial digital output will be a reclocked version of the
input signal regardless of whether the device is in SMPTE, DVB-ASI or
Data-Through mode.
When set LOW, the serial digital output will be a buffered version of the
input signal in all modes.
RSV
–
–
GS1561
Connect to CORE_VDD through 2.2kΩ.
71
MASTER/SLAVE
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to determine the input / output selection for the DVB_ASI, SD/HD,
RC_BYP and SMPTE_BYPASS pins.
When set HIGH, the GS1560A is set to operate in master mode where
DVB_ASI, SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS
become status signal output pins set by the device. In this mode, the
GS1560A will automatically detect, reclock, deserialize and process SD
SMPTE, HD SMPTE, or DVB-ASI input data.
When set LOW, the GS1560A is set to operate in slave mode where
DVB_ASI, SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS
become control signal input pins. In this mode, the application layer must
set these external device pins for the correct reception of either SMPTE or
DVB-ASI data. Slave mode also supports the reclocking and deserializing
of data not conforming to SMPTE or DVB-ASI streams.
72
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
73, 74
75
VCO, VCO
VCO_GND
Analog
–
Input
Differential inputs for the external VCO reference signal. For single ended
devices such as the GO1525, VCO should be AC coupled to VCO_GND.
VCO is nominally 1.485GHz.
Output
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1525. This pin is an output.
Should be isolated from all other grounds.
27360 - 8 September 2005
17 of 80
GENNUM [ GENNUM CORPORATION ]
