GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
66
CANC
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The CANC signal will be HIGH when the device has detected VANC or
HANC data in the chroma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal will
be HIGH when VANC or HANC data is detected in the chroma video
stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
67
FW_EN/DIS
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used in
the extraction and generation of TRS timing signals, in automatic video
standards detection, and in manual switch line lock handling.
When set LOW, the internal flywheel is disabled and TRS correction and
insertion is unavailable.
69
PCLK
–
Output
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
HD 10-bit mode
SD 20-bit mode
SD 10-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
PCLK = 148.5MHz or 148.5/1.001MHz
PCLK = 13.5MHz
PCLK = 27MHz
27360 - 8 September 2005
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GENNUM [ GENNUM CORPORATION ]
