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GS1561-CFE3 参数 Datasheet PDF下载

GS1561-CFE3图片预览
型号: GS1561-CFE3
PDF下载: 下载PDF文件 查看货源
内容描述: GS1560A / GS1561 HD - LINX -R II双率解串器 [GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer]
分类和应用: 存储静态存储器
文件页数/大小: 80 页 / 1307 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS1560A/GS1561 Data Sheet  
Table 1-1: Pin Descriptions (Continued)  
Pin  
Name  
Timing  
Type  
Description  
Number  
21  
SDO_EN/DIS  
Non  
Input  
GS1560A  
Synchronous  
CONTROL SIGNAL INPUT  
Signal levels are LVCMOS/LVTTL compatible.  
Used to enable or disable the serial digital output loop-through stage.  
When set LOW, the serial digital output signals SDO and SDO are  
disabled and become high impedance.  
When set HIGH, the serial digital output signals SDO and SDO are  
enabled.  
NC  
GS1561  
No Connect.  
22  
CD_GND  
Power  
GS1560A  
Ground connection for the serial digital cable driver. Connect to analog  
GND.  
NC  
GS1561  
No Connect.  
23, 24  
SDO, SDO  
Analog  
Output  
GS1560A  
Serial digital loop-through output signal operating at 1.485Gb/s,  
1.485/1.001Gb/s, or 270Mb/s.  
The slew rate of these outputs is automatically controlled to meet SMPTE  
292M and 259M specifications according to the setting of the SD/HD pin.  
NC  
GS1561  
No Connect.  
25  
RESET_TRST  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
Used to reset the internal operating conditions to default settings and to  
reset the JTAG test sequence.  
Host Mode (JTAG/HOST = LOW)  
When asserted LOW, all functional blocks will be set to default conditions  
and all input and output signals become high impedance, including the  
serial digital outputs SDO and SDO.  
Must be set HIGH for normal device operation.  
NOTE: When in slave mode, reset the device after the SD/HD input has  
been initially configured, and after each subsequent SD/HD data rate  
change.  
JTAG Test Mode (JTAG/HOST = HIGH)  
When asserted LOW, all functional blocks will be set to default and the  
JTAG test sequence will be held in reset.  
When set HIGH, normal operation of the JTAG test sequence resumes.  
26  
JTAG/HOST  
Non  
Input  
CONTROL SIGNAL INPUT  
Synchronous  
Signal levels are LVCMOS/LVTTL compatible.  
Used to select JTAG Test Mode or Host Interface Mode.  
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are  
configured for JTAG boundary scan testing.  
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are  
configured as GSPI pins for normal host interface operation.  
27360 - 8 September 2005  
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