This sum is then truncated as shown in the GF9101A Block
diagram. The sum then passes through a variable delay
along with the ZERO and NEGATE signals. The variable
delay is provided so that complementary sums from
cascaded GF9101A’s may be added together in the
pipelined output stage. The ZERO signal zeros the sum and
the NEGATE signal negates the sum.
PIPELINE_OUT or the registered PIPELINE_IN. The result is
then registered at PIPELINE_OUT. When using one
GF9101A, this configuration can be used to add two partial
filter sums from the A and B registers.
Another application is to use the PIPELINE_IN port for
adding DC offset or SYNC and BURST signals (i.e. for 4:2:2
to 4ƒ
SC
rate conversion). To do this, clock in the SYNC and
BURST signals from an external PROM connected to the
PIPELINE_IN.
Up to three GF9101A’s may be cascaded to form larger
filters by connecting PIPELINE_OUT from one of the
GF9101A devices to the PIPELINE_IN of another.
GF9101A
2.2 Pipelined Output Stage
The calculated filter sum from the adder tree and delay
enters into the pipelined output stage. Figure 5 shows the
block diagram for the pipelined structure. FB_SEL
determines whether the sum is added to the current
FILTER–SUM
PIPELINE–IN
20
PROM
R
20
0
1
20
+
20
R
PIPELINE–OUT
FB–SEL
CLK–IN
R
GF9101A
Fig. 5 Block Diagram for Pipelined Output Stage
CLK_IN
FILTER_SUM
XXX
SUM 1
SUM 2
XXX
SUM 3
XXX
PIPELINE_IN
003H
FB_SEL
XXX
PIPELINE_OUT
SUM 1
SUM 1
+
SUM 2
XXX
003H
+
SUM 3
XXX
Fig. 6 Timing Diagram for the Pipelined Output Stage
8
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GENNUM [ GENNUM CORPORATION ]
