2. FILTER ARCHITECTURE
For the following discussion on filter architecture, refer to the GF9101A Block diagram and Figure 4.
+10.0
+10.0
DATA _A_IN
ENA
TO NEXT TAP
A REG
R
+10.0
B REG
+10.0
DATA_B_IN
TO NEXT
TAP
R
ENB
1
0
R
R
SEL A/B
–
C REG
+10.0
ENC
+10.0
SIGNED /
UNSIGNED
MODE A
MODE B
0
1
MULT
MODE
REG
CONFIGURATION
REGISTER
+10.0 / ±9.0
108 x12
COEF
REG
±0.11
±0.11
7
COEF
REG
R
COEF ADDR
–
±10.11
MULT
REG
±10.11
TO ADDER
Fig. 4 Tap Cell (1-12)
2.1 Coefficient Multiplication and Addition Stage
MODE A and MODE B are separate, static control signals
which determine signed/unsigned for A or B input data
respectively. They are common to all taps. When using the
GF9101A as a 23 or 24-tap filter (combining REG_A and
REG_B to get a single filter output), MODE A and MODE B
should be in the same state. If not, a signed/unsigned
mismatch occurs.
Two shift registers, A and B, are used to shift input data
through the GF9101A. They can be used as two 12-tap
filters or as one 23-tap filter.
If DATA_B_SEL is set low during configuration, then two 12-
tap filters are initialized. Data applied at DATA_A_IN enters
at tap 1 and exits from tap 12, while data applied at
DATA_B_IN enters at tap 12 and exits from tap 1.
Use caution when using the GF9101A as two separate
filters with MODE A and MODE B in different states. In this
case, data entering REG_A is signed/unsigned while in
REG_B it is the opposite. If ENC is low and SEL_A/B
changes state, a signed/unsigned mismatch occurs. To
avoid an error under these circumstances, always make
ENC high after a SEL_A/B, state change.
If DATA_B_SEL is set high during configuration, then a
23-tap filter is initialized. Data applied at DATA_A_IN enters
at tap 1, reverses direction at tap 12 (bypasses REG_12B)
and exits from tap 1 on DATA_B_OUT, while DATA_B_IN is
disabled.
ENA and ENB control the shifting of the input data. The C
register holds the next set of 12 input values to be applied
to the multipliers.
The input values in the C register are multiplied by the
coefficient values in the COEF register and the result enters
an adder tree. The coefficients that enter the COEF register
are stored in the internal RAM and are selected by the
externally controlled COEF_ADDR (6-0) bus, which is
common to all taps. The non-truncated sum of taps 1
through 12 is at the output of the adder tree.
If ENC is high, SEL_A/B determines whether the A or B shift
register data enters the C register. SEL_A/B also determines
whether the MODE A or MODE B control signal enters the
MULT_MODE register. The value in the MULT_MODE
register determines whether the input data to the multiplier
is recognized as signed or unsigned.
7
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