DATA_A_IN
CLK_IN
0
1
2
3
4
5
6
7
8
9
10
11
ENA
ENB
B
A
B
A
B
A
B
A
B
A
B
A
SEL_A/B
COEF_ADDR
(6 - 0)
00
H
ENC
LOAD_EN
ZERO
CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 8 Timing Diagram for a 23-Tap Odd-Symmetric Filter
Assuming that the data A0 to A21 has already been shifted
into the filter registers, the data A22 enters DATA_A_IN by
clocking ENA and ENB (see Figure 9a). During the first
CLK_IN rising edge, the data in the A registers (A22 to A11)
are selected by SEL_A/B. They are then multiplied by the
coefficients C0 to C11 in memory location 0,
COEF_ADDR 00H.
The resulting products are passed through the adder tree
and the delay (4 CLK_IN cycles in total). The two resulting
sums are added in the pipeline section of the filter. FB_SEL
selects PIPELINE_IN during CLK_IN period 5, at which time
a DC offset could be introduced at PIPELINE_IN to be
added to the sum. During CLK_IN period 6, FB_SEL selects
PIPELINE_OUT and the final filter sum is calculated and
passed through to PIPELINE_OUT.
During the second CLK_IN rising edge, the data in the B
registers (A0 to A10) are selected by SEL_A/B. They are
then multiplied by the coefficients C0 to C10 in memory
location 0, COEF_ADDR 00H (see Figure 9b).
DATA A IN
–
–
A
A
A
11
A
A
21
DATA A IN
20
12
22
A
A
A
11
A
A
– –
20
12
22
21
A
A
A
DATA B OUT
A
2
10
1
0
–
–
A
A
A
DATA B OUT
A
2
10
1
0
–
–
x
C
x
x
x
x
11
C
C
1
C
2
10
C
0
x
x
10
x
C
x
x
C
11
C
C
1
C
2
0
Σ
Σ
PIPELINED
ADDER
PIPELINED
ADDER
(A x C ) + (A x C ) + (A x C ) +...+(A x C ) + (A x C
)
22 21 20 12 10 11 11
0
1
2
+
(A x C ) + (A x C ) + (A x C ) +...+(A x C
)
(A x C ) + (A x C ) + (A x C ) +...+(A x C ) + (A x C
)
0
0
1
1
2
2
10 10
22 21 20 12 10 11 11
0
1
2
Fig. 9b Data Flow Diagram for a 23 Tap Odd-Symmetric Filter
(After Second CLK_IN Rising Edge)
Fig. 9a Data Flow Diagram for a 23 Tap Odd-Symmetric Filter
(After First CLK_IN Rising Edge)
10
522 - 15 - 02
GENNUM [ GENNUM CORPORATION ]
