3.3 Asymmetric Filter
Table 10: Internal RAM Address & Contents for a 24-Tap
Asymmetric Filter
The GF9101A can be used as a 24-tap asymmetric filter by
configuring it in the same way as the even-symmetric case.
The difference is in the memory locations since the
asymmetric case uses 24 different coefficients (two sets of
filter coefficients). The filter coefficients and the memory
locations are shown in Table 10.
COEF_ADDR (6-0)
MEMORY CONTENTS
00H
01H
First set of 12 coefficients, C0 to C11
Second set of 12 coefficients, C23 to C12
The timing diagram is shown in Figure 11. The data flow
diagrams are shown in Figures 11a and 11b.
DATA_A_IN
0
1
2
3
4
5
6
7
8
9
10
CLK_IN
ENA
ENB
SEL_A/B
B
A
B
A
B
A
B
A
B
A
H
B
COEF_ADDR
(6-0)
01
00
00
01
01
01
H
H
01
00
00
00
01
H
H
H
H
H
H
H
H
ENC
LOAD_EN
ZERO
CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 11 Timing Diagram for a 24-Tap Asymmetric Filter
DATA A IN
DATA
A IN
–
–
–
–
A
A
13
A
A
A
A
12
A
A
13
A
A
A
22
21
23
22
21
12
23
DATA B OUT
A
A
A
11
A
A
10
A
A
A
A
–
–
0
1
DATA B OUT
2
1
0
10
2
11
–
–
C
x
x
x
x
22
x
12
x
x
x
C
x
C
C
13
x
11
C
21
C
C
C
C
10
1
C
23
2
0
S
S
PIPELINED
ADDER
PIPELINED
ADDER
(A x C ) + (A x C ) + (A x C ) +...+(A x C ) + (A x C
)
(A x C ) + (A x C ) + (A x C ) +...+(A x C ) + (A x C
23 22 21 13 10 12
)
0
23 22 21 10 13 11 12
1
2
0
1
2
11
+
(A x C ) + (A x C ) + (A x C ) +...+(A x C ) + (A x C
)
23 22 21 13 10 12 11
0
1
2
Fig. 11b Data Flow Diagram for a 24-Tap Asymmetric Filter
Fig. 11a Data Flow Diagram for a 24-Tap Asymmetric Filter
12
522 - 15 - 02
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