GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted.
Figure 6.5 - Initiating an Ultra DMA Data-In Burst
Notes:
IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until
some time after they are driven by the device.
Figure 6.6 - Sustained Ultra DMA Data-In Burst
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