GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
Figure 6.10 - Initiating an Ultra DMA Data-Out Burst
Notes:
IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet
until some time after they are driven by the host.
Figure 6.11 - Sustained Ultra DMA Data-Out Burst
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