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MBM29LV400TC-70PFTN 参数 Datasheet PDF下载

MBM29LV400TC-70PFTN图片预览
型号: MBM29LV400TC-70PFTN
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ( 512K ×8 / 256K ×16 )位 [4M (512K X 8/256K X 16) BIT]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 58 页 / 560 K
品牌: FUJITSU [ FUJITSU ]
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MBM29LV400TC-70/-90/-12/MBM29LV400BC-70/-90/-12  
Table 8 MBM29LV400TC/BC Extended Command Definitions  
Bus  
Write  
First Bus  
Second Bus  
Write Cycle  
Third Bus  
Fourth Bus  
Read Cycle  
Command  
Sequence  
Write Cycle  
Write Cycle  
Cycles  
Req'd  
Addr  
Data  
Addr  
2AAH  
555H  
Data  
Addr  
Data  
Addr  
Data  
Word  
Byte  
Word  
Byte  
555H  
AAAH  
XXXH  
XXXH  
555H  
Set to  
Fast Mode  
3
2
AAH  
55H  
20H  
AAAH  
Fast Program  
*1  
A0H  
90H  
PA  
PD  
Word  
XXXH  
XXXH  
XXXH  
XXXH  
Reset from  
2
4
F0H *3  
Fast Mode *1  
Byte  
Word  
Byte  
Extended  
Sector  
Protect *2  
XXXH  
60H  
SPA  
60H  
SPA  
40H  
SPA  
SD  
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).  
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected  
sector addresses.  
*1 This command is valid while Fast Mode.  
*2 This command is valid while RESET= VIH.  
*3 This data " 00H" is also acceptable.  
Command Definitions  
Device operations are selected by writing specific address and data sequences into the command register.  
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the  
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and  
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both  
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that  
commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.  
Read/Reset Command  
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset  
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor  
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command  
register contents are altered.  
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required  
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no  
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read  
Characteristics and Waveforms for the specific timing parameters.  
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