MBM29LV400TC-70/-90/-12/MBM29LV400BC-70/-90/-12
Table 7 MBM29LV400TC/400BC Standard Command Definitions
Fourth Bus
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Sixth Bus
Bus
Write
Read/Write
Cycle
Command
Sequence
Write Cycle Write Cycle
Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Read/Reset
Read/Reset
Autoselect
Program
1
3
3
4
6
6
XXXH F0H
—
—
—
—
—
RA
—
—
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555H
AAH
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
55H
55H
55H
55H
55H
F0H
90H
A0H
80H
80H
AAAH
555H
AAH
—
—
AAAH
555H
AAH
PA
PD
—
—
AAAH
555H
AAH
555H
AAAH
555H
AAAH
2AAH
555H
2AAH
555H
555H
AAAH
Chip Erase
Sector Erase
AAH
AAH
55H
55H
10H
30H
AAAH
555H
AAH
SA
AAAH
Sector Erase Suspend
Sector Erase Resume
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)
Notes: 1. Address bits A11 to A17 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
2. Bus operations are defined in Tables 2 and 3.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.
5. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A10
6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
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