MB90610A Series
Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
1
1
1
2
4
4
4
0
0
0
(c) word (SP) ← (SP) –2, ((SP)) ← (A)
(c) word (SP) ← (SP) –2, ((SP)) ← (AH)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(c) word (SP) ← (SP) –2, ((SP)) ← (PS)
3
5
4
(SP) ← (SP) –2n, ((SP)) ← (rlst)
*
*
*
POPW A
1
1
1
2
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
–
–
3
3
4
0
0
0
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
2
5
4
–
–
–
–
–
–
–
*
*
*
JCTX @A
1
Context switch instruction
–
–
*
*
*
*
*
*
*
–
14
0
6× (c)
AND
OR
CCR, #imm8
CCR, #imm8
2
2
byte (CCR) ← (CCR) and imm8
byte (CCR) ← (CCR) or imm8
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
3
3
0
0
0
0
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
0
0
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
2
2+
2
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
1
1
0
0
0
0
0
0
2+ (a)
1
MOVEA A, eam
2+
word (A) ←eam
*
1+ (a)
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
0
0
0
0
1
MOV
MOV
A, brgl
brg2, A
2
2
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
0
0
0
0
*
1
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank –
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR : 2 states
*2: 7 + 3 ¥ (pop count) + 2 ¥ (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 ¥ (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count ¥ (c), or push count ¥ (c)
*1: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
86
FUJITSU [ FUJITSU ]
