MB90610A Series
■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER
ASSIGNMENTS TO INTERRUPT SOURCES
I2OS
sup-
port
Interrupt vector
Number Address
Interrupt control register
Interrupt source
ICR
—
Address
Reset
×
×
×
#08
#09
#10
#11
08H
09H
0AH
0BH
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
—
—
INT 9 instruction
Exception
—
—
—
External interrupt #0
ICR00
0000B0H
External interrupt #1
External interrupt #2
External interrupt #3
External interrupt #4
External interrupt #5
External interrupt #6
UART0 • transmit complete
External interrupt #7
#13
#15
#17
#19
#21
#23
#24
#25
0DH
0FH
11H
13H
15H
17H
18H
19H
FFFFC8H
FFFFC0H
FFFFB8H
FFFFB0H
FFFFA8H
FFFFA0H
FFFF9CH
FFFF98H
ICR01
ICR02
ICR03
ICR04
ICR05
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
ICR06
0000B6H
ICR07
ICR08
0000B7H
0000B8H
UART1 • transmit complete
PPG #0
#26
#27
#28
#29
1AH
1BH
1CH
1DH
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
×
×
PPG #1
16-bit reload timer #0
ICR09
ICR10
ICR11
0000B9H
0000BAH
0000BBH
16-bit reload timer #1
#30
#31
#33
#34
#35
#37
#39
#42
1EH
1FH
21H
22H
23H
25H
27H
2AH
FFFF84H
FFFF80H
FFFF78H
FFFF74H
FFFF70H
FFFF68H
FFFF60H
FFFF54H
A/DC measurement complete
UART2 • transmit complete
Timebase timer interval interrupt
UART2 • receive complete
UART1 • receive complete
UART0 • receive complete
Delayed interrupt generation module
×
×
ICR12
ICR13
ICR14
ICR15
0000BCH
0000BDH
0000BEH
0000BFH
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request).
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request).
× : indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS.
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