MB90480/485 Series
(16) Chip Select Output Timing
Parameter
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym-
bol
Condi-
Pin name
Unit Remarks
tions
Min
Max
Chip select output valid time
→RD↓
CS0 to CS3,
RD
tSVRL
tSVWL
tRHSV
tWHSV
⎯
⎯
⎯
⎯
tCP* / 2 − 7
⎯
ns
ns
ns
ns
Chip select output valid
time→WR↓
CS0 to CS3,
WRH, WRL
tCP* / 2 − 7
tCP* / 2 − 17
tCP* / 2 − 17
⎯
⎯
⎯
RD↑→chip select output valid
time
RD,
CS0 to CS3
WR↑→chip select output
valid time
WRH, WRL,
CS0 to CS3
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
t
SVRL
2.4 V
RD
0.8 V
t
RHSV
2.4 V
A23 to A16
CS0 to CS3
0.8 V
2.4 V
0.8 V
D15 to D00
Read data
t
SVWL
t
WHSV
2.4 V
WRH, WRL
D15 to D00
0.8 V
Unde-
fined
Write data
Note : Due to the configuration of the internal bus, the chip select output signals are changed simultaneously and
therefore may cause the bus conflict conditions. AC cannot be warranted between the ALE output signal
and the chip select output signal.
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