MB90480/485 Series
(13) I2C Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Standard-mode
Parameter
Symbol
Condition
Unit
Min
Max
SCL clock frequency
fSCL
0
100
kHz
Hold time (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
⎯
µs
When power supply voltage of
external pull-up resistance is 5.5 V
R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R = 1.6 kΩ, C = 50 pF*2
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
4.7
4.0
⎯
⎯
µs
µs
tHIGH
Set-up time (repeated) START
condition SCL↑→SDA↓
tSUSTA
4.7
0
⎯
µs
µs
Data hold time
SCL↓→SDA↓↑
tHDDAT
3.45*3
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1 ≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
250*4
200*4
⎯
⎯
ns
ns
external pull-up resistance is 3.6 V
fCP*1 ≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2
Data set-up time
SDA↓↑→SCL↑
tSUDAT
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1 > 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
fCP*1 > 20 MHz, R = 1.6 kΩ, C = 50 pF*2
Set-up time for STOP condition
SCL↑→SDA↑
When power supply voltage of
external pull-up resistance is 5.5 V
R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R = 1.6 kΩ, C = 50 pF*2
tSUSTO
4.0
4.7
⎯
⎯
µs
µs
Bus free time between a STOP and
START condition
tBUS
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock Timing”.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA and SCL set-up time”.
Note : VCC = VCC3 = VCC5
105
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