Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
Figure 6.21 Typical SPI Master Timing
Time
t1
Description
SCLK period
Minimum
39.68
Typical
41.67
Maximum
Unit
ns
t2
SCLK high period
19.84
20.84
21.93
21.93
3
ns
t3
SCLK low period
19.84
20.84
ns
t4
SCLK driving edge to MOSI/SS
-1.5
ns
MISO setup time to sample
SCLK edge
t5
t6
6.5
ns
ns
MISO hold time from sample
SCLK edge
0
Table 6.14 SPI Master Timing
55
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