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VNC2-48Q1B-TRAY 参数 Datasheet PDF下载

VNC2-48Q1B-TRAY图片预览
型号: VNC2-48Q1B-TRAY
PDF下载: 下载PDF文件 查看货源
内容描述: [Vinculum-II Embedded Dual USB Host Controller IC]
分类和应用:
文件页数/大小: 88 页 / 2234 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Datasheet  
Vinculum-II Embedded Dual USB Host Controller IC  
Version 1.7  
Document No.: FT_000138 Clearance No.: FTDI#143  
64 Pin  
Package  
48 Pin  
Package  
32 Pin  
Package  
Name  
Type  
Description  
Available Available Available  
pins  
pins  
pins  
12, 16,  
20, 25,  
29, 40,  
44, 48,  
52, 58,  
62  
12,16,  
21, 32,  
36, 42,  
46  
Master Out Slave In  
12, 24,  
30  
spi_m_mosi  
Output  
Synchronousdata from master to slave  
13, 17,  
22, 26,  
31, 41,  
45, 49,  
55, 59,  
63  
13, 18,  
22, 33,  
37, 43,  
47  
14, 25,  
31  
Master In Slave Out  
spi_m_miso  
Input  
Synchronousdata from slave to master  
14, 18,  
23, 27,  
32, 42,  
46, 50,  
56, 60,  
64  
14, 19,  
23, 34,  
38, 44,  
48  
Active low slave select 0 from masterto  
slave 0  
15, 26,  
32  
spi_m_ss_0#  
Output  
11, 15,  
19, 24,  
28, 39,  
43, 47,  
51, 57,  
61  
11, 15,  
20, 31,  
35, 41,  
45  
Active low slave select 1 from masterto  
slave 1  
11, 23  
29  
spi_m_ss_1#  
Output  
Table 6.13 SPI Master Signal Names  
The main purpose of the SPI Master block is to transfer data between an external SPI interface and the  
VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus.  
An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select  
signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK.  
The master always supplies the first byte, which is called a command byte. After this the desired number  
of data bytes are transferred before the transaction is terminated by the master de-asserting slave  
select.  
The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of  
each byte spi_tx_done and spi_rx_full_int are set. Figure 6.21 Typical SPI Master Timing and  
Table 6.14 SPI Master Timing show an example of this.  
54  
Copyright © Future Technology Devices International Limited  
 
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