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chec½ed to see i½ the data read was accepted. ½ ½0½ level on ½½I Data ½ut means that the data write was accepted. ½
½1½ indicates that the internal ½u½½er is ½ull½½ and the write should ½e repeated. ½emem½er that C½ must ½e held low ½or at
least one cloc½ period ½e½ore ½eing ta½en high again to continue with the ne½t read or write cycle.
Figure 4 - ½½I ½lave Data Timing Diagrams
T1
SPICLK
T2
T3
SPICS /
SPI DATA IN
T6
T4
T5
SPI DATA OUT
T7
Ta½le 4 - ½½I ½lave Data Timing
Time
T1
T2
T3
T4
T½
T6
T7
Description
½½ICLK ½eriod
½½ICLK High
½½ICLK Low
Input ½etup Time
Input Hold Time
½utput Hold Time
½utput Valid Time
Min
83
20
20
10
10
2
-
Typical
-
-
-
-
-
-
-
Max
-
-
-
-
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
Ta½le ½ - ½tatus ½egister (½DD = ½1½)
Bit
0
1
2
3
4
½
6
7
Description
RXF#
TXE#
-
-
RXF IRQEn
TXE IRQEn
-
-
VDrive2 Vinculum VNC1L Module
Datasheet Version 0.99
© Future Technology Devices International Ltd. 2007
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
