VDIP1 参数 Datasheet PDF下载

2.6 SPI Interface Signal Descriptions and Timing Diagrams

Page 

Ta�½le 8 - Data and Control �½�½us �½ignal Mode �½ptions - �½PI Inter�½ace

Pin No.

6

8

9

10

Name

�½CLK

�½DI

�½D�½

C�½

Type

Input

Input

�½utput

Input

Description

�½PI Cloc�½ input�½�½ 12MHz ma�½imum.

�½PI �½erial Data Input

�½PI �½erial Data �½utput

�½PI Chip �½elect Input

Figure �½ - �½PI �½lave Data �½ead Cycle

�½/W �½DD D7

�½PICLK

�½PI C�½

�½PI Data In

1

�½PI Data �½ut

�½tart

D6

D�½

D4

D�½

D2

D1

D0

1

0

From �½tart - �½PI C�½ must �½e held high �½or the entire read cycle�½�½ and must �½e ta�½en low �½or at least one cloc�½ period

�½�½�½�½�½�½ �½h�½ �½�½�½�½�½ �½�½ �½�½mpl�½�½�½�½�½ Th�½ �½�½�½�½�½�½ b�½�½ �½�½ �½�½I �½�½�½�½ I�½ �½�½ �½h�½ R/W b�½�½ - �½�½pu�½�½�½�½g �½ ‘1�½ h�½�½�½�½ �½ll�½�½�½ �½�½�½�½ �½�½ b�½ �½�½�½�½�½ �½�½�½�½m

the chip. The ne�½t �½it is the address �½it�½�½ �½DD�½�½ which is used to indicate whether the data register (�½0�½) or the status

register (�½1�½) is read �½rom. During the �½PI read cycle a �½yte o�½ data will start �½eing output on �½PI Data �½ut on the ne�½t

�½l�½�½k �½y�½l�½ �½�½�½�½�½�½ �½h�½ �½�½�½�½�½�½�½�½ b�½�½�½�½ M�½�½�½ �½�½�½�½�½�½�½ A�½�½�½�½�½ �½h�½ �½�½�½�½ h�½�½ b�½�½�½ �½l�½�½k�½�½ �½u�½ �½�½ �½h�½ �½h�½p�½�½ �½h�½ �½�½�½�½u�½ �½�½ �½�½I �½�½�½�½

�½ut should �½e chec�½ed to see i�½ the data read is new data. �½ �½0�½ level here on �½PI Data �½ut means that the data read

is new data. �½ �½1�½ indicates that the data read is old data�½�½ and the read cycle should �½e repeated to get new data.

�½emem�½er that C�½ must �½e held low �½or at least one cloc�½ period �½e�½ore �½eing ta�½en high again to continue with the

ne�½t read or write cycle.

Figure 6 - �½PI �½lave Data Write Cycle

�½/W �½DD D7

�½PICLK

�½PI C�½

�½PI Data In

�½PI Data �½ut

1

0

0

D6

D�½

D4

D�½

D2

D1

D0

�½tart

From �½tart - �½PI C�½ must �½e held high �½or the entire write cycle�½�½ and must �½e ta�½en low �½or at least one cloc�½ period

�½�½�½�½�½�½ �½h�½ �½�½�½�½�½�½ �½�½ �½�½mpl�½�½�½�½�½ Th�½ �½�½�½�½�½�½ b�½�½ �½�½ �½�½I �½�½�½�½ I�½ �½�½ �½h�½ R/W b�½�½ - �½�½pu�½�½�½�½g �½ ‘0�½ h�½�½�½�½ �½ll�½�½�½ �½�½�½�½ �½�½ b�½ �½�½�½�½�½�½�½�½

to the chip. The ne�½t �½it is the address �½it�½�½ �½DD�½�½ which is used to indicate whether the data register (�½0�½) or the status

VDIP1 Vinculum VNC1L Prototyping Module

Datasheet Version 0.92

© Future Technology Devices Intl Ltd. 2006-2007

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