2.5 Parallel FIFO Interface Signal Descriptions and Timing Diagrams
Page
Ta�½le �½ - Data and Control �½�½us �½ignal Mode �½ptions - Parallel FIF�½ Inter�½ace
Pin No.
6
8
9
10
11
12
1�½
14
1�½
16
17
19
Name
D0
D1
D2
D�½
D4
D�½
D6
D7
RXF#
TX�½#
R�½#
W�½
Type
I/�½
I/�½
I/�½
I/�½
I/�½
I/�½
I/�½
I/�½
�½�½TP�½T
�½�½TP�½T
INP�½T
INP�½T
Description
FIF�½ Data �½�½us �½�½it 0
FIF�½ Data �½�½us �½�½it 1
FIF�½ Data �½�½us �½�½it 2
FIF�½ Data �½�½us �½�½it �½
FIF�½ Data �½�½us �½�½it 4
FIF�½ Data �½�½us �½�½it �½
FIF�½ Data �½�½us �½�½it 6
FIF�½ Data �½�½us �½�½it 7
When high�½�½ do not read data �½rom the FIF�½. When low�½�½ there is data availa�½le in the FIF�½ which can
b�½ �½�½�½�½�½ by �½�½�½�½�½b�½�½g R�½# l�½�½�½�½ �½h�½�½ h�½gh �½g�½�½�½�½
When high�½�½ do not write data into the FIF�½. When low�½�½ data can �½e written into the FIF�½ �½y stro�½ing
W�½ high�½�½ then low.
�½�½�½bl�½�½ �½h�½ �½u�½�½�½�½�½�½�½ FIFO �½�½�½�½ by�½�½ �½�½ �½0�½�½�½�½7 �½h�½�½ l�½�½�½ F�½�½�½h�½�½ �½h�½ �½�½x�½ FIFO �½�½�½�½ by�½�½ (�½�½ �½v�½�½l-
�½bl�½) �½�½�½�½m �½h�½ �½�½�½�½�½�½v�½ FIFO bu�½�½�½�½�½ �½h�½�½ R�½# g�½�½�½ �½�½�½�½m h�½gh �½�½ l�½�½�½
Writes the data �½yte on the D0...D7 pins into the transmit FIF�½ �½u�½�½er when W�½ goes �½rom high to low.
Figure �½ - FIF�½ �½ead Cycle
T6
RXF#
T1
T5
T2
RD#
T3
T4
Valid Data
D[7...0]
Ta�½le 6 - FIF�½ �½ead Cycle Timings
Time
T1
T2
T�½
T4
T�½
T6
Description
�½D �½ctive Pulse Width
�½D to �½D Pre-Charge Time
�½D �½ctive to Valid Data*
Valid Data Hold Time �½rom �½D Inactive*
R�½ I�½�½�½�½�½v�½ �½�½ RXF#
�½XF Inactive �½�½ter �½D Cycle
Min
�½0
�½0 + T6
20
0
0
80
Max
-
-
�½0
-
2�½
-
Unit
ns
ns
ns
ns
ns
ns
* Load = �½0pF
VDIP1 Vinculum VNC1L Prototyping Module
Datasheet Version 0.92
© Future Technology Devices Intl Ltd. 2006-2007
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
