Page 10
register (�½1�½) is written to. During the �½PI write cycle a �½yte o�½ data can �½e input to �½PI Data In on the ne�½t cloc�½ cycle
�½�½�½�½�½�½ �½h�½ �½�½�½�½�½�½�½�½ b�½�½�½�½ M�½�½�½ �½�½�½�½�½�½�½ A�½�½�½�½�½ �½h�½ �½�½�½�½ h�½�½ b�½�½�½ �½l�½�½k�½�½ �½�½ �½�½ �½h�½ �½h�½p�½�½ �½h�½ �½�½�½�½u�½ �½�½ �½�½I �½�½�½�½ Ou�½ �½h�½ul�½ b�½
chec�½ed to see i�½ the data read was accepted. �½ �½0�½ level on �½PI Data �½ut means that the data write was accepted. �½
�½1�½ indicates that the internal �½u�½�½er is �½ull�½�½ and the write should �½e repeated. �½emem�½er that C�½ must �½e held low �½or at
least one cloc�½ period �½e�½ore �½eing ta�½en high again to continue with the ne�½t read or write cycle.
Figure 7 - �½PI �½lave Data Timing Diagrams
T1
�½PICLK
T2
T�½
�½PIC�½ /
�½PI D�½T�½ IN
T6
T4
T�½
�½PI D�½T�½ �½�½T
T7
Ta�½le 9 - �½PI �½lave Data Timing
Time
T1
T2
T�½
T4
T�½
T6
T7
Description
�½PICLK Period
�½PICLK High
�½PICLK Low
Input �½etup Time
Input Hold Time
�½utput Hold Time
�½utput Valid Time
Min
8�½
20
20
10
10
2
-
Typical
-
-
-
-
-
-
-
Max
-
-
-
-
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
Ta�½le 10 - �½tatus �½egister (�½DD = �½1�½)
Bit
0
1
2
�½
4
�½
6
7
Description
RXF#
TX�½#
-
-
RXF IRQ�½�½
TX�½ IRQ�½�½
-
-
VDIP1 Vinculum VNC1L Prototyping Module
Datasheet Version 0.92
© Future Technology Devices Intl Ltd. 2006-2007
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
