Document Reference No.: FT_000237
V2DIP2-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 152
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3.8 Parallel FIFO Interface-Synchronous Mode
The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two
hardware flow control signals, an output enable and a clock out.
The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 3.7 and an
additional two signals detailed in Table 3.9.
Available Pins
Name
Type
Output
Output
Description
FIFO Output Enable
J2-8, J2-4, J1-7, J1-14, J1-19, J2-18,
J2-13
fifo_oe#
J2-7, J1-4, J1-8, J1-16, J1-20, J2-17
fifo_clkout
FIFO Output Enable
Table 3.9 - Data and Control Bus Signal Mode Options – Synchronous FIFO mode
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