DS_FT311D USB ANDROID HOST IC Datasheet
Version 1.0
Document No.: FT_000660 Clearance No.: FTDI# 305
In this mode:
• When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
• When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
• When CPHA = 0, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
• When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
Mode CPOL CPHA
0
1
2
3
0
0
1
1
0
1
0
1
Table 5.3 - Clock Phase/Polarity Modes
Figure 5-3 - SPI CPOL CPHA Function
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