DS_FT311D USB ANDROID HOST IC Datasheet
Version 1.0
Document No.: FT_000660 Clearance No.: FTDI# 305
If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that
address. The master then continues in either transmit or receive mode (according to the read/write bit it
sent), and the slave continues in its complementary mode (receive or transmit, respectively).
The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-
low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL
high.
If the master has to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit.
(In this situation, the master is in master transmit mode and the slave is in slave receive mode.)
If the master has to read from the slave then it repeatedly receives a byte from the slave, the master
sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive
mode and the slave is in slave transmit mode.)
The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain
control of the bus for another transfer (a "combined message").
I²C defines three basic types of message, each of which begins with a START and ends with a STOP:
.
.
.
Single message where a master writes data to a slave;
Single message where a master reads data from a slave;
Combined messages, where a master issues at least two reads and/or writes to one or more
slaves
In a combined message, each read or write begins with a START and the slave address. After the first
START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits,
which is how slaves know the next transfer is part of the same message.
Please refer to the I2C specification for more information on the protocol.
5.5 Serial Peripheral Interface – SPI Modes
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
FT311D has one master module and one slave module. Both the SPI master and slave module has four
signals – clock, slave select, MOSI (master out – slave in) and MISO (master in – slave out). Table 5.2
lists how the signals are named in each module.
Module
Signal Name
Type
Description
spi_s_clk
spi_s_ss#
Input
Input
Clock input
Active low slave select input
Master out serial in
SPI Slave
spi_s_mosi
spi_s_miso
spi_m_clk
Input
Output
Output
Output
Input
Master in slave out
Clock output – master
spi_m_mosi
spi_m_miso
spi_m_ss_0#
Master out slave in - master
Master in slave out - master
Active low slave select 0 from master to slave 0
SPI
Master
Output
Table 5.2 SPI Signal Names
The SPI slave protocol by default does not support any form of handshaking. It is simply transferring 8
bit data.
5.5.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 5.3 summarizes these modes and available interface and
Figure 5-3 is the function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
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